military and industrial temperature ranges idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable 1 january 2004 military and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-2630/9 features: ? std., a, c, and d grades ? low input and output leakage 1a (max.) ? cmos power levels ? true ttl input and output compatibility: ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) ? high drive outputs (-15ma i oh , 48ma i ol ) ? meets or exceeds jedec standard 18 specifications ? military product compliant to mil-std-883, class b and desc listed (dual marked) ? power off disable outputs permit "live insertion" ? available in the following packages: ? industrial: soic, qsop ? military: cerdip, lcc functional block diagram idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable description: the idt54/74fct377t is an octal d flip-flop built using an advanced dual metal cmos technology. the idt54/74fct377t has eight edge- triggered, d-type flip-flops with individual d inputs and o outputs. the common buffered clock (cp) input loads all flip-flops simultaneously when the clock enable ( ce ) is low. the register is fully edge-triggered. the state of each d input, one set-up time before the low-to-high clock transition, is transferred to the corresponding flip-flop?s o output. the ce input must be stable only one set-up time prior to the low-to-high transition for predictable operation. ce cp d cp q d 0 o 0 d cp q d 1 o 1 d cp q d 2 o 2 d cp q d 3 o 3 d cp q d 4 o 4 d cp q d 5 o 5 d cp q d 6 o 6 d cp q d 7 o 7
military and industrial temperature ranges 2 idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. output and i/o terminals only. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. lcc top view cerdip/ soic/ qsop top view 1 2 3 4 5 7 9 6 8 10 11 12 13 14 15 16 17 18 19 20 o 6 d 7 d 6 o 5 d 5 c e d 0 o 0 v c c o 3 g n d c p o 4 d 4 index d 1 o 1 d 3 o 2 d 2 o 7 2 3 1 16 15 14 11 19 18 20 17 13 12 5 6 7 4 8 9 10 d 1 o 0 d 0 v cc o 1 d 3 o 2 d 2 o 3 gnd o 7 o 6 d 7 d 6 o 5 o 4 d 5 d 4 cp ce pin description pin names description d 0 ? d 7 data inputs ce clock enable (active low) o 0 ? o 7 data outputs c p clock pulse input function table (1) inputs outputs operating mode cp ce do load ?1? lh h load ?0? ll l hold h x no change h h x no change note: 1. h = high voltage level h = high voltage level one setup time prior to the low-to-high clock transition l = low voltage level l = low voltage level one setup time prior to the low-to-high clock transition x = don't care = low-to-high clock transition
military and industrial temperature ranges idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable 3 dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial : t a = ?40c to +85c, v cc = 5.0v 5%; military: t a = ?55c to +125c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 2.7v ? ? 1 a i il input low current (4) v cc = max. v i = 0.5v ? ? 1 a i i input high current (4) v cc = max., v i = v cc (max.) ? ? 1 a v ik clamp diode voltage v cc = min., i n = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max. (3) , v o = gnd ?60 ?120 ?225 ma v oh output high voltage v cc = min. i oh = ?6ma mil. 2.4 3.3 ? v v in = v ih or v il i oh = ?8ma ind. i oh = ?12ma mil. 2 3 ? v i oh = ?15ma ind. v ol output low voltage v cc = min. i ol = 32ma mil. ? 0.3 0.5 v v in = v ih or v il i ol = 48ma ind. i off input/output power off v cc = 0v, v in or v o - 4.5v ? ? 1 a leakage (5) v h input hysteresis ? ? 200 ? mv i cc quiescent power v cc = max. ? 0.01 1 ma supply current v in = gnd or v cc notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. the test limit for this parameter is 5a at t a = -55c. 5. this parameter is guaranted but not tested.
military and industrial temperature ranges 4 idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input; (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of ? i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2+ f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = output frequency n i = number of outputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply v cc = max. ? 0.5 2 ma current ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max., outputs open v in = v cc ? 0.15 0.25 ma/ current (4) ce = gnd v in = gnd mhz one input toggling 50% duty cycle i c total power supply v cc = max., outputs open v in = v cc ? 1.5 3.5 ma current (6) f cp = 10mhz v in = gnd ce = gnd v in = 3.4v ? 2 5.5 one bit toggling v in = gnd f i = 5mhz 50% duty cycle v cc = max., outputs open v in = v cc ? 3.8 7.3 (5) f cp = 10mhz, 50% duty cycle v in = gnd ce = gnd v in = 3.4v ? 6 16.3 (5) eight bits toggling v in = gnd f i = 2.5mhz 50% duty cycle notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 54fct377t 54/74fct377at 54/74fct377ct 74fct377dt mil. ind. mil. ind. mil. ind. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf 2 15 2 7.2 2 8.3 2 5.2 2 5.5 2 4.4 ns t phl cp to qx r l = 500 ? t su set-up time high or low 3 ? 2 ? 2 ? 2 ? 2 ? 2 ? ns dx to cp t h hold time high or low 2.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1 ? ns dx to cp t su set-up time high or low 4 ? 3.5 ? 3.5 ? 3.5 ? 3.5 ? 3 ? ns ce to cp t h hold time high or low 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 0 ? ns ce to cp t w cp pulse width high or low 7 ? 8 ? 7 ? 6 ? 7 ? 3 ? ns switching characteristics over operating range
military and industrial temperature ranges idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable 5 pulse generator r t d.u.t . v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
military and industrial temperature ranges 6 idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable ordering information idt xx temp. range fct xxxx device type xx package x process fast cmos octal d flip-flop with clock enable 377t 377at 377ct 377dt so q industrial options small outline ic quarter-size small outline package d l military options cerdip leadless chip carrier blank b industrial mil-std-883, class b 54 74 ? 55 c to +125 c ? 40 c to +85 c corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com 6/26/2002 updated as per pdns logic-00-07 and logic-01-04 data sheet document history
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